1. Cross Reference
The subject matter related to this application is disclosed in a pending U.S. patent application Ser. No. 500,965, filed on Mar. 29, 1990, invented by Shuji Murakami et al., assigned to the same applicant.
2. Field of the Invention
The present invention relates to a circuit structure for repairing a defective memory cell (faulty bit) in a semiconductor memory device.
3. Description of the Background Art
A semiconductor memory device is generally provided with a spare row and a spare column in the memory cell array for repairing a defective memory cell (faulty bit) from the stand point of yield and the like.
Such a redundancy scheme for repairing a defective memory cell is disclosed in U.S. Pat. No. 4,389,715 entitled "Redundancy Scheme For a Dynamic RAM" issued on Jun. 21, 1985, invented by Eaton et al. and assigned to Inmos Corporation; an article entitled "32 K and 16 K Static MOS RAMs using Laser Redundancy Techniques" by R. J. Smith et al. in 1982 IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb. 12, 1982, pages 252 and 253; and an article entitled "An Ultralow Power 8 K.times.8 bit Full CMOS RAM with a Six-Transistor Cell" by K. Ochii et al. in IEEE Journal of Solid-State Circuits, Vol. SC-17 No. 5, October, 1982, pages 798 to 803.
FIG. 1 shows a schematic overview of a memory device comprising the redundancy scheme disclosed by R. J. Smith et al. This memory device comprises a SRAM (static random access memory) cell.
Referring to FIG. 1, a conventional semiconductor memory device comprises a memory cell array 1 having a plurality of memory cells MC arranged in n rows and m columns. Memory cell array 1 is provided with n rows R1-Rn each having a row of memory cells connected thereto and m columns C1-Cm each having a column of memory cells connected thereto. Memory cell array 1 is also provided with a spare row SR and a spare column SC in predetermined positions (the 1st row and the m+1-th column in FIG. 1) for repairing a defective memory cell. Each of rows R1-Rn is connected to the output signal lines (output nodes) X1-Xn of row decoder 3. The row decoder 3 decodes externally applied X address signals (row address signals) A0-Ak, to select one line out of the output signal lines X1-Xn according to the decoded result.
Each of columns C1-Cm is connected to the output signal lines (the column selecting signal transmission line) Y1-Ym of a column decoder 6. Column decoder 6 decodes externally applied Y address signals (column address signals) B0-Bj to select one line out of the output signal lines Y1-Ym according to the decoded result and activates the selected output signal line.
The output signal lines Y1-Ym of column decoder 6 are connected to the gates of column selecting gates 90a and 90b for selectively connecting columns C1-Cm to the common data line (not shown) in response to the output signal of column decoder 6. Column selecting gate 90a connects bit line BLp of column Cp (P=1-m) to the common data line, whereas column selecting gate 90b connects the complementary bit line Blp of column Cp to the complementary common data line. The group of gates formed of column selecting gates 90a and 90b implement a column selecting gate 9.
The output signal of column decoder 6 is transmitted to column selecting gate 9 via fuses f1-fm. Fuses f1-fm can be melted by a laser beam, for example. A high resistor r is provided in parallel with fuses f1-fm to maintain the gate potential of column selecting gates 90a and 90b connected to the melted fuse at ground potential level when an associated fuse is melted.
For the purpose of repairing the row including the faulty bit, a program circuit 30, a spare row decoder 31, and a spare row driver SXD are provided. Program circuit 30 stores the address of the row comprising the faulty bit. Program circuit 30 generally comprises a structure similar to that of a unit row decode circuit forming row decoder 3. The storage of the address of the row comprising the faulty bit in program circuit 30 is often carried out by melting the fuses included therein by a laser beam.
The spare row decoder 31 provides a signal NED which brings row decoder 3 to a non-activation state, and also a spare row selecting signal, in response to the activation signal from program circuit 30. The spare row driver SXD is responsive to the spare row selecting signal from spare row decoder 31 to drive spare row SR, whereby spare row SR attains a selected state (activation state).
A program circuit 61 and a spare column decoder 60 are provided for the purpose of selecting spare column (redundancy column) SC. Program circuit 61 stores the address of the column comprising the defective memory cell to provide an activation signal when external Y address signal B0-Bj designates the column including the defective memory cell. Spare column decoder 60 provides a signal which selects the spare column SC in response to the activation signal from program circuit 61. The operation thereof will be explained hereinafter.
First, the operation in the case where a defective memory cell does not exist will be explained. Row decoder 3 decodes externally applied X address signals A0-Ak to provide a signal which selects one of rows R1-Rn to one line of output signal lines X1-Xn. This causes the potential in row Ri (the selected row is Ri) to rise, whereby row Ri attains the selected state. The information in the memory cell MC connected to this selected row Ri is read out to each columns C1-Cm.
Column decoder 6 decodes externally applied Y address signals B0-Bj, whereby the signal potential of one of the output signal lines Y1-Ym is raised in response to the Y address decode signal. The selected column is assumed to be Ci. The potential of the output signal line Yi of column decoder 6 rises to turn on the column selecting gates 90a and 90b, whereby column Ci is connected to the common data line. Then, the data of the memory cell located at the intersection of the selected row Ri and the selected column Ci is read out or written. This data reading is carried out using a sense amplifier or the like which is not shown.
The case where a defective memory cell exists in the memory cell connected to row Ri will be considered hereinafter. The presence/absence of a defective memory cell is detected by a function test of the semiconductor memory device. At this time, the address of row Ri where the defective memory cell is present will be written into program circuit 30 for row repairing. The writing of the address to program circuit 30 is carried out by melting the fuses with a laser, as is mentioned above.
When the externally applied X address signal A0-Ak designates row Ri, program circuit 30 is activated to operate spare row decoder 31. The spare row decoder 31 in the operation state brings spare row SR to the selected state via spare row driver SXD, and also activates signal NED to bring row decoder 3 to a non-activation state. This replaces row Ri comprising the defective memory cell with the spare row SR, whereby the repair of the faulty row Ri is performed.
The case where a defective memory cell exists in column Ci is considered hereinafter. Similar to the repair of the row, the address of column Ci comprising the defective memory cell is written into program circuit 61 for column repair by disconnection of a fuse, for example. At this time, fuse fi connected to the output signal line Yi for selecting column Ci comprising the defective memory cell is also disconnected, as shown in FIG. 2, whereby the faulty column Ci is detached from column decoder 6. The output signal line Yi corresponding to the faulty column Ci is connected to a reference potential, for example, ground potential, via resistance r, whereby the faulty column Ci will always be at the non-selected state.
When the externally applied Y address signals B0-Bj designates column Ci, spare column decoder 60 operates via program circuit 61 to select spare column SC. Although column decoder 6 also operates at this time, the faulty column Ci is at the non-selected state because the output signal line Yi is detached from column decoder 6. By the output of spare column decoder 60, spare column SC is selected to replace column Ci comprising the defective memory cell with spare column SC. Thus, the repair of the faulty column Ci is performed.
The faulty bit repairing circuit implemented in the above manner in a conventional semiconductor memory device requires a program circuit for storing the faulty row or the faulty column, a spare row decoder for driving a spare row, and a spare column decoder for driving a spare column, leading to a problem of increasing the chip area.
The programming of the faulty row address or the faulty column address in the program circuit is generally carried out by disconnecting the fuse. However, the number of fuses comprised in the program circuit is great, as shown in the examples of the aforementioned Smith et al. or Ochii et al. literatures, increasing the number of fuse disconnections for programming the faulty row or faulty column. Because the programming of the faulty row or the faulty column is such that is carried out by each chip, reduction in throughput during the repairing work, and error in the fuse disconnecting position is likely to occur. This results in the problem that the repair success rate is reduced to lower the yield of the semiconductor memory device.
At the time of row repairing when a faulty row (Xi) is selected, the row decoder is non-activated by signal NED from the spare row decoder, as shown in FIG. 3. Because the row decoder is first activated, and then non-activated in response to signal NED, the faulty row including the defective memory cell will also be once selected. To prevent the effect of the selection of the row comprising the defective memory cell, it was necessary to connect the selected memory cell to the common data line after the faulty row is definitely in the non-selected state, that is, after the signal potential of the selected row is established. This results in the problem that the access time TA becomes longer.
The output signal line of the column decoder is provided with a resistor of high resistance for the purpose of maintaining the faulty column at the nonselected state definitely. Because this resistor of high resistance is provided in every column decoder output signal line, current will flow through this resistor of high resistance at the time of column selection, resulting in a problem that current consumption is increased.